Aggressive scaling of transistor dimensions with each technology generation has resulted in increased integration density and improved device performance. Unfortunately, leakage current increases with the reduction of the device dimensions. Increased integration density along with the increased leakage necessitates ultra-low power operation in the present power-constrained design environment. The power requirement for battery operated devices such as cell phones and medical devices is even more stringent. Reducing the supply voltage reduces the dynamic power quadratically and leakage power linearly to the first order. Hence, supply voltage scaling has remained the major focus of the low power design. This has resulted in circuits operating at a supply voltage lower than the threshold voltage of a transistor. However, as the supply voltage is reduced, the sensitivity of the circuit parameters to process variations increases. Process variations limit the circuit operation in the sub-threshold region, particularly in memories, as discussed, for example, in the following paper: A. Bhavnagarwala et al., “The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability,” IEEE Journal of Solid-State Circuits, vol. 36, pp. 658-665, April 2001. Embedded cache memories are expected to occupy 90% of the total die area of a system-on-a-chip. Nano-scaled SRAM bitcells having minimum sized transistors are vulnerable to inter-die as well as intra-die process variations. Intra-die process variations include random dopant fluctuation (RDF), line edge roughness (LER) etc. This may result in a threshold voltage mismatch between the adjacent transistors in a memory cell. Coupled with inter-die and intra-die process variations, lower supply voltage operation results in various memory failures, i.e., read failure, hold failure, access time failure and write failure. See, e.g., S. Mukhopadhyay et al., “Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS,” IEEE Transactions on Computer Aided Design, pp. 1859-1880, December 2005. Memory failure probability is predicted to be higher in the future technology nodes.
Adaptive circuit techniques such as source biasing, dynamic VDD have been proposed to improve the process variation tolerance, as discussed by H. Kawaguchi et al. in “Dynamic Leakage Cutoff Scheme For Low-Voltage SRAMs,” VLSI Circuit Symposium, pp. 140-141, June 1998. Self-calibration techniques to achieve low voltage operation while keeping the failure probability under control are also proposed. See, e.g., S. Ghosh et al, “Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-Scaled SRAM,” Proc. of 43rd Design Automation Conference, pp. 971-976, July 2006.
A 6-transistor (6T) cell which uses a cross-coupled inverter pair is the “de facto” memory bitcell used in current SRAM designs. A typical 6T cell has four MOSFET transistors arranged to form the cross-coupled inverters, and two additional MOSFET transistors which serve to control access to the cell during read and write operations. One such example is shown in U.S. Pat. No. 7,328,413 to Kim et al., issued Feb. 5, 2008, to the assignee of the present invention. The patent discloses a 6T SRAM cell with an added sleep transistor to reduce leakage and increase read stability. FIG. 1 herein also illustrates a typical 6T cell configuration, with the cross-coupled inverters and with the two access transistors electrically connecting the inverter pair to respective bit lines (BL), and with a word line (WL) that controls the access transistors. Different types of SRAM bitcells have been proposed to improve the memory failure probability at a given supply voltage (FIG. 1). 6T and 7T bitcells utilize differential read operation while 5T, 8T and 10T bitcells employ single ended reading scheme. 8T and 10T cells use an extra sensing circuit for reading the cell contents; achieving improved read SNM. A comparison of various SRAM bitcells is shown in TABLE 1.
TABLE 1Comparison of various SRAM bitcellsSr. No.5T6T7T8T10TReadSingleDifferentialDifferentialSingleSingleEndedEndedEnded#WL11122#BL12233Area0.81—1.31.66#PMOS22223#NMOS222 or 323in ReadPath
Further details regarding 5T, 7T, 8T and 10T bitcells may be found in the following papers, respectively:                1. Carlson et al., “A High Density, Low Leakage, 5T SRAM for Embedded Caches,” Proc. of 30th European Solid State Circuits Conference, pp. 215-218, September 2004.        2. R. Aly et al., “Novel 7T SRAM Cell for Low Power Cache Design,” Proc. of IEEE SOC Conference, pp. 171-174, 2005.        3. Chang et al., “Stable SRAM Cell Design for the 32 nm Node and Beyond,” Symposium on VLSI Technology, pp. 128-129, 2005.        4. B. H. Calhoun et al., “A 256 kb Sub-threshold SRAM in 65 nm CMOS,” Proc. of International Solid State Circuits Conference, pp. 628-629 & 678, February 2006.        
In spite of efforts by various groups, a need remains for improvements in SRAM technology. More specifically, a need remains for mechanisms and techniques for improving the stability of the inverter pair in a SRAM bitcell operating at lower supply voltages.